ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
Figure 25. Power Supply Management: Dual Power Supply
STAND-ALONE
SUPPLY
USBVIT+
USBVIT-
VPLLmin48
SUPPLY
VOLTAGES
USBVDD
PLG INTERRUPT
REQUEST
RESET
S/W
STATUS
RESET
STAND-ALONE 1 2
PROCESSING
RESET
USB MODE
PROCESS.
1
2
RST
STAND-ALONE MODE
PROCESSING
RESET
USBEN
HI-Z
S/W Reset
S/W Reset
ON
HI-Z
VDD pin
voltage
VIT+(LVD)
STAND-ALONE
PLL
ON/OFF
PLL OFF
USB MODE
PLL ON
48 MHz
SIGNAL
CLOCK
SOURCE
NO CLOCK
CRYSTAL (12MHz)
UFINNDEED3 STABLE 48 MHz 4
PLL
STAND-ALONE
VIT-(LVD)
PLL OFF
NO CLOCK
CRYSTAL (12MHz)
1. Interrupt processing
2. Finish current processing
3. PLL start-up time (automatically controlled by hardware following a software reset)
4. PLL running with frequency in the range of 48 to 24 MHz (see section 13.3.3 on page 131)
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