ST7282B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7282B5

ROM FROM EPROM

STMicroelectronics 

ST7282A5 - ST7282B5 - ROM FROM EPROM

3 TESTING

Pin VPP/TEST is used for testing the device. For

normal operation pin VPP/TEST has to be con-

nected to VSS or has to be left open. An internal

pull down resistor of about 100k is integrated to

select normal operation mode if pin VPP/TEST is

not connected.

The testmodes are for SGS THOMSON internal

use only!

4 PIN DESCRIPTION

4.1 Connection diagram

Figure 10. Connection Diagram ( top view ) for the 80 pin quad flat pack

PC6/AIN

PC7/AIN

STOP/OSCOUT

OSCIN

S16/PD7

S15/PD6

S14/PD5

S13/PD4

S12/PD3

S11/PD2

S10/PD1

S09/PD0

VPP/TEST

S8/PF7

S7/PF6

S6/PF5

S5/PF4

S4/PF3

S3/PF2

S2/PF1

S1/PF0

BP16/S-0/PG7

BP15/S-1/PG6

BP14/S-2/PG5

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

1

64

2

63

3

62

4

61

5

60

6

59

7

58

8

57

9

56

10

55

11

54

12

13

ST 7282 B5

53

52

14

51

15

50

16

49

17

48

18

47

19

46

20

45

21

44

22

43

23

42

24

41

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PB1/AIN

PB0/AIN

PA7/DOUT/AIN

PA6/SDA/AIN

PA5/SCL/AIN

PA4/AIN

PA3/AIN

PA2/AIN

PA1/CP2/AIN

PA0/CP1/AIN

RESET

VSSA

VDDA

RDSREF

MPX

RDSFIL

PE5/S22

RDSCOMP/PE4/S21

S20/PE3

S19/PE2

S18/PE1

S17/PE0

VLCD1/5

VLCD2/5

Family

ST7

Issuer Ref.

PG-RO

Chrono

97115

7282A5B5

March 26, 1997

CONDIAG.DS4

Previous Ref

Edition

Target C

Page 21/23

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