ST7FMC1M2T3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

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ST7FMC1M2T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.7 LINSCI Clock Tolerance

LINSCI Clock Tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no

characters have been transmitted for a relatively

long time), the maximum tolerated deviation of the

LINSCI clock is +/-15%.

If the deviation is within this range then the LIN

Synch Break is detected properly when a new re-

ception occurs.

Consequently, the clock frequency should not vary

more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start

bit, so that when receiving 10 bits (one start bit, 1

data byte, 1 stop bit), the clock deviation should

not exceed 3.75%.

10.5.9.8 Clock Deviation Causes

The causes which contribute to the total deviation

are:

This is made possible by the fact that masters

send 13 low bits for the LIN Synch Break, which

can be interpreted as 11 low bits (13 bits -15% =

11.05) by a “fast” slave and then considered as a

LIN Synch Break. According to the LIN specifica-

tion, a LIN Synch Break is valid when its duration

is greater than tSBRKTS = 10. This means that the

LIN Synch Break must last at least 11 low bits.

Note: If the period desynchronization of the slave

is +15% (slave too slow), the character “00h”

which represents a sequence of 9 low bits must

not be interpreted as a break character (9 bits +

15% = 10.35). Consequently, a valid LIN Synch

break must last at least 11 low bits.

LINSCI Clock Tolerance when Synchronized

When synchronization has been performed, fol-

lowing reception of a LIN Synch Break, the LINS-

CI, in LIN mode, has the same clock deviation tol-

erance as in SCI mode, which is explained below:

– DTRA: Deviation due to transmitter error.

Note: The transmitter can be either a master

or a slave (in case of a slave listening to the

response of another slave).

– DMEAS: Error due to the LIN Synch measure-

ment performed by the receiver.

– DQUANT: Error due to the baud rate quantiza-

tion of the receiver.

– DREC: Deviation of the local oscillator of the

receiver: This deviation can occur during the

reception of one complete LIN message as-

suming that the deviation has been compen-

sated at the beginning of the message.

– DTCL: Deviation due to the transmission line

(generally due to the transceivers)

All the deviations of the system should be added

and compared to the LINSCI clock tolerance:

DTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%

During reception, each bit is oversampled 16

times. The mean of the 8th, 9th and 10th samples

is considered as the bit value.

Figure 71.Bit Sampling in Reception Mode

RDI LINE

Sample

clock

sampled values

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16

7/16

One bit time

130/309

1

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