ST7MC2N6T3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7MC2N6T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

MOTOR CONTROLLER (Cont’d)

the MCOMP and MTIM register is enabled before

a write access in the MCOMP register. This means

that if the SC bit is set and no write access is done

after in the MCOMP register, no CS commutation

event will occur.

In Speed Measurement mode, when using encod-

er or tachogenerator speed sensors (i.e. both

TES[1:0] bits in the MPAR register are not reset

and the input detection block is set-up to process

sensor signals), motor speed can be measured

but it is not possible drive a motor in six-step

mode, either sensored or sensorless.

Speed Measurement mode is useful for motors

supplied with 3-phase sinewave-modulated PWM

signals:

– AC induction motors,

– Permanent Magnet AC (PMAC) motors (al-

though it needs three position sensors, they

can be handled just like tachogenerator sig-

nals).

This mode uses only part of the Delay Manager’s

resources. For more details refer to “Speed Meas-

urement Mode” on page 180.

Table 37. Switched and Autoswitched modes

SWA

bit

0

1

Commutation Type

Switched mode

Autoswitched mode

MCOMP User

access

Read/Write

Read/Write

10.6.7.1 Switched Mode

This feature allows the motor to be run step-by-

step. This is useful when the rotor speed is still too

low to generate a BEMF. It can also run other

kinds of motor without BEMF generation such as

induction motors or switch reluctance motors. This

mode can also be used for autoswitching with all

computation for the next commutation time done

by software (hardware multiplier not used) and us-

ing the powerful interrupt set of the peripheral.

In this mode, the step time is directly written by

software in the commutation compare register

Table 38. Step Update

MCOMP. When the MTIM timer reaches this value

a commutation occurs (C event) and the MTIM

timer is reset.

At this time all registers with a preload function are

loaded (registers marked with (*) in Section

10.6.13). The CI bit of MISR is set and if the CIM

bit in the MIMR register is set an interrupt is gener-

ated.

The MTIM timer prescaler (Step ratio bits ST[3:0]

in the MPRSR register) is user programmable. Ac-

cess to this register is not allowed while the MTIM

timer is running (access is possible only before the

starting the timer by means of the CKE bit) but the

prescaler contents can be incremented/decre-

mented at the next commutation event by setting

the RMI (decrement) or RPI (increment) bits in the

MISR register. When this method is used, at the

next commutation event the prescaler value will be

updated but also all the MTIM timer-related regis-

ters will be shifted in the appropriate direction to

keep their value. After it has been taken into ac-

count, (at commutation) the RPI or RMI bit is reset

by hardware. See Table 38.

Only one update per step is allowed, so if both RPI

and RMI bits are set together by software, this

does not affect the MISR register: the write access

to these two bits together is not taken into account

and the previous state is kept. This means that if

either RPI or RMI bit was set before the write ac-

cess of both bits at the same time, this bit (RPI or

RMI) is kept at 1. If none of them was set before

the simultaneous write access, none of them will

be set after the write access.

In switched mode, BEMF and demagnetization de-

tection are already possible in order to pass in au-

toswitched mode as soon as possible but Z and D

events do not affect the timer contents.

In this mode, if an MTIM overflow occurs, it re-

starts counting from 0x00h and the OI overflow

flag in the MCRC register is set if the TES[1:0] bits

= 00.

Caution: In this mode, MCOMP must never be

written to 0.

Mode

x

Switched

Autoswitched

Speed

measure

TES[1:0]

xx

00

00

01 10 11

CKE SWA Clock

bit bit State

0 x Disabled

1 0 Enabled

1 1 Enabled

1 x Enabled

Read

Ratio Increment

(Slow Down)

Ratio Decrement

(Speed-Up)

Write the ST[3:0] value directly in the MPRSR register

Set RPI bit in the MISR reg- Set RMI bit in the MISR reg-

Always ister till next commutation ister till next commutation

possible

Automatically updated according to MZREG value

169/309

1

Share Link: