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ST7MC2N6 View Datasheet(PDF) - STMicroelectronics

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ST7MC2N6 Datasheet PDF : 309 Pages
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CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 137. PLL And Clock Detector Signal Start Up Sequence
OSCIN
PLLEN
(PLL and CKD)
PLL CLOCK
LOCK
2)
CKSEL
fCLK
16Mhz
t lock
OSCIN Clock
PLL clock
3)
ST7MC1xx/ST7MC2xx
fVCO= 6 Mhz
1)
CSSD
CSSIE 4)
INTERRUPT
t setup
t hold
Notes:
1. Lock does not go low without resetting the PLLEN bit.
2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of tlock must have
elapsed.
3. 2 clock cycles are missing after CKSEL = 1
4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1).
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