ST7MC1xx/ST7MC2xx
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL Input low level voltage
VIH Input high level voltage
Vhys Schmitt trigger voltage hysteresis 2)
0.7xVDD
1
0.3xVDD
V
V
VOL Output low level voltage 3)
VDD=5V
IIO=+5mA
IIO=+2mA
0.5
1.2
V
0.2
0.5
IIO
Driving current on RESET pin
2
mA
RON Weak pull-up equivalent resistor
VIN=VSS, VDD=5V
50
80
150
kΩ
tw(RSTL)out Generated reset pulse duration
Internal reset sources
30
μs
th(RSTL)in External reset pulse hold time 4)
2.5
μs
tg(RSTL)in Filtered glitch duration 5)
450
ns
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network protects the device against parasitic resets.
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