ST7FMC1M7T3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7FMC1M7T3
STMicroelectronics
ST7FMC1M7T3 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the Wait
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the Halt modes (see column “Exit from
Halt” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting Halt
mode, the first one serviced can only be an inter-
rupt with exit from Halt mode capability and it is se-
lected through the same decision process shown
in Figure 21.
Note: If an interrupt, that is not able to Exit from
Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 22 and Figure 23 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 23. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, MCES. The software priority
is given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
SOFTWARE
PRIORITY
I1
I0
LEVEL
MCES
IT0
IT1
IT1
IT2
IT3
RIM
IT4
MAIN
11 / 10
MAIN
10
3
11
3
11
3
11
3
11
3
11
3
11
3/0
Figure 23. Nested Interrupt Management
IT1
IT2
RIM
MAIN
11 / 10
MCES
IT0
IT4
IT4
IT1
IT3
SOFTWARE
PRIORITY
I1
I0
LEVEL
IT2
MAIN
10
3
11
3
11
2
00
1
01
3
11
3
11
3/0
42/309
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