ST7FMC1M7T3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7FMC1M7T3
STMicroelectronics
ST7FMC1M7T3 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
The Halt mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see section 6.4 on page 37 for more de-
tails on the MCCSR register).
The MCU can exit Halt mode on reception of either
a specific interrupt (see Table 8, “Interrupt Map-
ping,” on page 44) or a RESET. When exiting Halt
mode by means of a RESET or an interrupt, the
oscillator is immediately turned on and the 256 or
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 31).
When entering Halt mode, the I[1:0] bits in the CC
register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In Halt mode, the main oscillator is turned off caus-
ing all internal processing to be stopped, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the option byte. The HALT instruction when ex-
ecuted while the Watchdog system is enabled, can
generate a Watchdog RESET (see section 14.1 on
page 290 for more details).
Figure 30. Halt Timing Overview
256 OR 4096 CPU
RUN HALT CYCLE DELAY
RUN
HALT
INSTRUCTION
[MCCSR.OIE=0]
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 31. Halt Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
WDGHALT 1)
0
DISABLE
1
WATCHDOG
RESET
OSCILLATOR OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from Halt mode (such as external interrupt). Refer
to Table 8, “Interrupt Mapping,” on page 44 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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