ST92195C/D View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92195C/D

48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

STMicroelectronics 

ST92E195C/D-ST92T195C/D - ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

PIN CAPACITANCE

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Symbol

Parameter

Conditions

CIO

Pin Capacitance Digital Input/Output

Value

Unit

min

max

10

pF

CURRENT CONSUMPTION

(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)

Symbol

Parameter

Conditions

IDD1

IDDA1

IDD2

IDDA2

Run Mode Current

Run Mode Analog Current

(pin VDDA)

HALT Mode Digital Current

HALT Mode Analog Current

(pin VDDA)

Notes 1,2; all ON

Timing Controller ON

Notes 1,4

Notes 1,4

Value

Unit

min

typ.

max

70

100

mA

35

50

mA

10

100

µA

10

100

µA

Notes:

1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.

The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.

2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.

All peripherals working including Display.

3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.

The TDSRAM interface and the Slicers are working; the Display controller is not working.

4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.

EXTERNAL INTERRUPT TIMING TABLE

(VDD = 5V ± 10%, TA = 0°C +70° C, Cload = 50 pF, INTCLK = 12 MHz, Push-pull output configuration, un-

less otherwise specified)

N° Symbol

Parameter

1 TwLR

2 TwHR

3 TwHF

4 TwLF

Low Level Minimum Pulse Width in Rising

Edge Mode

High Level Minimum Pulse Width in Rising

Edge Mode

High Level Minimum Pulse Width in Falling

Edge Mode

Low Level Minimum Pulse Width in Falling

Edge Mode

Value (Note)

OSCIN Divided

by 2 Min.

OSCIN Not Divided

by 2 Min.

Unit

Min.

2TpC+12

TpC+12

95 ns

2TpC+12

TpC+12

95 ns

2TpC+12

TpC+12

95 ns

2TpC+12

TpC+12

95 ns

Note: The value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period,

prescale value and number of wait cycles inserted.

The value right hand two columns show the timing minimum for an external clock at 24 MHz divided by 2, prescale value of zero and zero

wait status.

TpC = OSCIN clock period

239/249

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