ST92195D View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92195D

48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

STMicroelectronics 

ST92195C/D - INTERRUPTS

ARBITRATION MODES (Cont’d)

End of Interrupt Routine

The iret Interrupt Return instruction executes

the following steps:

– The Flag register is popped from system stack.

– If ENCSR is set, CSR is popped from system

stack.

– The PC high byte is popped from system stack.

– The PC low byte is popped from system stack.

– All unmasked Interrupts are enabled by setting

the CICR.IEN bit.

– The priority level of the interrupted routine is

popped from the special register (NICR) and

copied into CPL.

– If ENCSR is reset, CSR is used instead of ISR,

unless the program returns to another nested

routine.

The suspended routine thus resumes at the inter-

rupted instruction.

Figure 23 on page 49 contains a simple example,

showing that if the ei instruction is not used in the

interrupt service routines, nested and concurrent

modes are equivalent.

Figure 24 on page 50 contains a more complex ex-

ample showing how nested mode allows nested

interrupt processing (enabled inside the interrupt

service routinesi using the ei instruction) accord-

ing to their priority level.

Figure 24. Complex Example of a Sequence of Interrupt Requests with:

- Nested mode

- IEN set to 1 during the interrupt routine execution

Priority Level of

Interrupt Request

0

1

INT 0

CPL=0

INT0

CPL6 > CPL3:

INT6 pending

INTERRUPT 0 HAS PRIORITY LEVEL 0

INTERRUPT 2 HAS PRIORITY LEVEL 2

INTERRUPT 3 HAS PRIORITY LEVEL 3

INTERRUPT 4 HAS PRIORITY LEVEL 4

INTERRUPT 5 HAS PRIORITY LEVEL 5

INTERRUPT 6 HAS PRIORITY LEVEL 6

2

INT 2

INT 2

INT 2

CPL=2

CPL=2 INT6

CPL=2

3

ei

INT 3

CPL=3 INT2

INT2

4

INT3

ei

INT 4

INT4

CPL2 < CPL4:

CPL=4

5

INT 5

Serviced just after ei

ei

ei CPL=5

6

ei

INT5

INT 4

CPL=4

INT 5

CPL=5

INT 6

CPL=6

7 MAIN

CPL is set to 7

MAIN

CPL=7

50/249

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