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ST92T195 View Datasheet(PDF) - STMicroelectronics

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ST92T195 Datasheet PDF : 249 Pages
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ST92195C/D - TIMING AND CLOCK CONTROLLER
5 TIMING AND CLOCK CONTROLLER
5.1 FREQUENCY MULTIPLIERS
Three on-chip frequency multipliers generate the
proper frequencies for: the Core/Real time Periph-
erals, the Display related time base and the Slicer
over-sampling clock for the Teletext Data slicer.
For both the Core and the Display frequency mul-
tipliers, a 4 bit programmable feed-back counter
allows the adjustment of the multiplying factor to
the application need (a 4 MHz or 8 MHz crystal is
assumed).
Figure 32. Timing and Clock Controller Block Diagram
PXFM
Async.
Handler
MCFM
SLDIV2
Divide
by 2
Frequency
Multiplier
Hsync
Skew Corrector
SKHPLS
SKDIV2
Divide
Synchronized DOTCK / 2 to Display
by 2
(2X Pixel clock for 1X width characters)
SKWEN SKWL(3:0)
4 MHz real time Clock
Frequency
Multiplier
FMEN
FML(3:0)
(Synchronized DOTCK) SKDIV2
Divide
by 2
Divide
by 64
TXCF
Frequency
Multiplier
( x 777 )
SLIEN
to Teletext Display Storage RAM (TRI)
to CSYNC Controller,
SYNC Extractor, ..
48.56 MHz Clock
(Teletext SLicer)
OSCIN
Xtal
Oscillator
OSCOUT
FMEN
FMSL
Divide
by 2
Fimf
Asynch.
Handler
Main Clock Controller
Div-2
Prescaler
1 to 8
Memory Wait
BREQ
WFI
Clock
Control
MODER.5
ST9 Clock Control Unit (RCCU)
CPUCLK
INTCLK
VR02095A
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