STA320 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA320 Datasheet PDF : 37 Pages
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STA320
5.2.4 Channel Input Mapping
BIT
R/W
RST
NAME
DESCRIPTION
6
R/W
0
C1IM
0 – Processing channel 1 receives Left I2S Input
1 – Processing channel 1 receives Right I2S Input
7
R/W
1
C2IM
0 – Processing channel 2 receives Left I2S Input
1 – Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input
Mapping registers. This allows for flexibility in processing. The default settings of these registers map each
I2S input channel to its corresponding processing channel.
5.3 Configuration Register C(Address 02h)
D7
D6
D5
D4
OCRB
CSZ4
CSZ3
CSZ2
1
1
0
0
D3
CSZ1
0
D2
CSZ0
0
D1
OM1
1
D0
OM0
0
5.3.1 DDX Power Output Mode
BIT
R/W
RST
NAME
0
R/W
0
OM0
1
R/W
1
OM1
DESCRIPTION
DDX Power Output Mode: Selects configuration of DDX
output.
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
different output modes. The STA50x or STA51x recommended use is OM = 10.
Table 13. Output Modes
OM(1,0)
00
01
10
11
Output Stage – Mode
STA50x/STA51x – Drop Compensation
Discrete Output Stage – Tapered Compensation
STA50x/STA51x – Full Power Mode
Variable Drop Compensation (CSZx bits)
5.3.2 DDX Compensating Pulse Size Register
BIT
R/W
RST
NAME
DESCRIPTION
2
R/W
0
3
R/W
0
4
R/W
0
CSZ0
CSZ1
CSZ2
Contra Size Register: When OM(1,0) = 11, this register
determines the size of the DDX compensating pulse from 0
clock ticks to 31 clock periods.
5
R/W
0
CSZ3
6
R/W
1
CSZ4
Table 14. Compensating Pulse Size
CSZ(4..0)
00000
00001
…
11111
Compensating Pulse Size
0ns(0 tick) Compensating Pulse Size
10ns(1 tick) Clock period Compensating Pulse Size
…
310ns(31 tick) Clock period Compensating Pulse Size
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