STA321
I2C disabled (microless) mode
The input sampling frequency must be between 32 kHz and 48 kHz and the master clock
input (MCLK or XTI) must be 256 * fS.
The CMOS bridge FFX output is configured in line-out mode:
z left channel binary on OUT1
z right channel binary on OUT2
z zero signal binary (duty cycle 50%) on OUT3
z pop-free digital ramp active
z volume control not effective (always 0 dB)
z switching frequency 384 kHz.
The external amplifier FFX output is configured in BTL mode:
z left channel BTL (new ternary modulation) on EAPWM1 and EAPWM2
z right channel BTL (new ternary modulation) on EAPWM1 and EAPWM2
z volume control is effective
z switching frequency 384 kHz.
The headphone detection is disabled.
The CLKOUT pad is active at the PLL frequency of 2048 * fS.
Doc ID 15351 Rev 3
151/157