User-programmable settings
STA323WQS
8.10.3
PLL unlock indicator
Table 72. PLL unlock indicator
Bit
R/W
RST Name
Description
0: normal operation (PLL is in a locked state)
7
RO
0
PLLUL 1: PLL unlock is detected (due to probable
clock loss)
Under normal conditions (with the correct clock) the PLL is locked into an internal clocking
frequency. However, if the clock is insufficient or if it is abruptly lost, the PLL lock state is lost
and this information is relayed to the user via setting the PLLUL bit of the Status register
to 1. As soon as the PLL reverts back to a locked state, this bit is set to 0.
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