STE2004SDIE2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STE2004SDIE2

102 x 65 single-chip LCD controller/driver

STMicroelectronics 

STE2004S

Figure 32. Acknowledgment on the I2C-bus

START

SCLK FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

MSB

Bus interfaces

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

LR0070

4.1.1

Communication protocol

The STE2004S is an I2C slave. The access to the device is bi-directional as data write and

status read are allowed.

The STE2004S has four device addresses. All have the first 5 bits (01111) in common. The

two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs

to a logic 0 or logic 1.

To start the communication between the bus master and the slave LCD driver, the master

must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA

bus line (most significant bit first). This consists of the 7-bit device select code, and the 1-bit

read/write designator (R/W).

All slaves with the corresponding address acknowledge in parallel, while the rest ignore the

I2C-bus transfer.

Writing mode

When the R/W bit is set to logic 0, the STE2004S is set to be a receiver. After the slaves

acknowledge, one or more command word follows to define the status of the device.

A command word is composed of three bytes. The first is a control byte which defines the

Co and D/C values, the second and third are data bytes. The Co bit is the command MSB

and defines whether this command is followed by two data bytes and and another command

word, or if a stream of data follows (Co = 1 Command word, Co = 0 Stream of data). The

D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C

= 0 Command).

If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and

D/C =1, the following data byte is stored in the data RAM at the location specified by the

data pointer.

Every byte of a command word must be acknowledged by all addressed units.

After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside

the STE2004S display RAM starting at the address specified by the data pointer. The data

pointer is automatically updated after every byte written and in the end points to the last

RAM location written.

Every byte must be acknowledged by all addressed units.

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