Electrical characteristics
Table 28. AC operation
Symbol
Tr;DA
Tf;DA
Tr;DA
Tf;DA
TSU;STO
Cb
Cb
Parameter
Test condition
Rise time of SCLH signal Cb = 100pF(5) (6)
Fall time of SDAH signal Cb = 100pF(5) (6)
Rise time of SDAH signal Cb = 400pF(5) (6)
Fall time of SDAH signal Cb = 400pF(5) (6)
Setup time for STOP
condition
Cb = 100pF(5) (6)
Capacitive load for SDAH
and SCLH
Capacitive load for SDAH
+SDA line and SCLH
+SCL line
Parallel interface (Figure 73, Figure 74)
TCYC
TCLW
TCHW
TCLR
TCHR
TEWHW
TEWLW
TEWHR
TEWLR
TSU(A)
TH(A)
TSU1
TH1
TSU2
TH2
System cycle time
VDD1 = 1.7V;
read and write
Control low pulse width
(WR)
Control high pulse width
(WR)
Control low pulse width
(RD)
Control high pulse width
(RD)
Enable high pulse width
(Write)
Enable low pulse width
(Write)
Enable high pulse width
(Read)
Enable low pulse width
(Read)
Address set-up time
Address hold time
Data set-up time
Data hold time
Read access time
Output disable time
STE2004S
Min.
10
10
20
20
160
100
Typ.
Max.
Unit
ns
80
ns
ns
160
ns
ns
400
pF
400
pF
125
ns
20
ns
75
ns
40
ns
55
ns
60
ns
60
ns
60
ns
60
ns
10
ns
10
ns
30
ns
30
ns
40
ns
0
30
ns
68/79