STFPC320 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STFPC320

Front panel controller/driver with standby power management and real-time clock

STMicroelectronics 

STFPC320

4

Functional description

Functional description

The STFPC320 integrates the supply standby management functionality, remote control

decoder, a 28-bit VFD driver and a real-time clock (RTC). This device is meant to reduce the

standby power consumption of the whole front panel application and also to reduce

hardware/cost by integrating the above mentioned functions in a single chip.

By utilizing the standby function, the host processor and other ICs could be turned off, thus

reducing the system power consumption. The STFPC320 is able to wake-up the system

when programmed hotkeys are detected to signal that the full operation of the system is

required. The hotkeys could be entered to the system through the front panel keys or

through the infrared (IR) remote control. STFPC320 supports multiple remote control

protocols decoding by setting the appropriate register.

The integrated 28-bit VFD driver can drive up to 16 digits of display. Controlling of the

display is done through writing to a internal RAM. The 4 LED drivers allow indication of

operation of the system. 2-wire serial interface (I2C) completes the interfacing part between

host processor and STFPC320.

The STFPC320 integrates a a low-power serial RTC with a built-in 32.768kHz oscillator

(external crystal controlled). Eight bytes of the SRAM are used for the clock/calendar

function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of

SRAM provide status/ control of alarm, watchdog and square wave functions. Addresses

and data are transferred serially via a two line, bidirectional I2C interface. The built-in

address register is incremented automatically after each WRITE or READ data byte.

Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm

interrupts, watchdog timer and programmable Square Wave output. The eight clock address

locations contain the century, year, month, date, day, hour, minute, second and

tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year -

valid until year 2100), 30 and 31 day months are made automatically.

4.1

Reset

Reset is an active low input signal to the STFPC320. A negative pulse input on RESET_N

pin resets the STFPC320. Electrical specifications of this pin are identical to that of the logic

input pin.

Upon power-up, an internal power on reset circuit resets the whole chip. This occurs when

VDD is ramping up (at approximately 2.7 V) and the whole chip is initialized within 4 µs. This

time is much lesser than the typical VDD ramp-up time. It is recommended to tie the

RESET_N pin permanently by a pull-up resistor to VDD if reset to STFPC320 is not desired

during normal operation. For an initialization on power-up, a power-on-reset in STFPC320 is

sufficient to reset the entire STFPC320.

As soon as the 3.3 V supply to the chip is stable, the I2C bus of the STFPC320 is ready for

communication.

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