STLC3075(2005) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC3075
(Rev.:2005)

INTEGRATED POTS INTERFACE FOR HOME ACCESS GATEWAY AND WLL

STMicroelectronics 

STLC3075

Table 12. External Components @Gain Set = 0 (continued)

Name

Function

Formula

CTTX (3) Pulse metering cancellation

capacitor

CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]}

RLV Pulse metering level resistor

RLV = 63.3·103··α·VLOTTX

α = (|Zlttx + 2Rp|/|Zlttx|)

CS Pulse metering shaping capacitor CS = τ/(2⋅RLV)

CFL Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV)

Typ. Value

100nF 10% 10V (2)

@ Zlttx = 200Ω real

16.2kΩ @ VLOTTX = 170mVrms

100nF 10% 10V

@ τ = 3.2ms, RLV = 16.2kΩ

1.5nF 10% 10V

@fttx = 12kHz RLV = 16.2kΩ

Table 13. External Components @Gain Set = 1

Name

Function

Formula

RS Protection resistance image

RS = 25 ⋅ (2Rp)

ZAC Two wire AC impedance

ZAC = 25 ⋅ (Zs - 2Rp)

ZA (1) SLIC impedance balancing

network

ZA = 25 ⋅ Zs

ZB (1) Line impedance balancing

network

ZB = 25 ⋅ Zl

CCOMP AC feedback loop compensation fo = 250kHz

CCOMP = 2/(2π⋅fo⋅100⋅(RP))

CH Trans-Hybrid Loss frequency

compensation

CH = CCOMP

RTTX (3) Pulse metering cancellation

resistor

RTTX = 25Re (Zlttx+2Rp)

CTTX (3) Pulse metering cancellation

capacitor

CTTX = 1/25⋅2π⋅fttx⋅[-lm(Zlttx)]

RLV Pulse metering level resistor

RLV = 31.7·103··α·VLOTTX

α = (|Zlttx + 2Rp|/|Zlttx|)

CS Pulse metering shaping capacitor CS = τ/(2⋅RLV)

CFL Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV)

Typ. Value

2.55kΩ @ Rp = 50Ω

12.5kΩ 1% @ Zs = 600Ω

15kΩ 1% @ Zs = 600Ω

15kΩ 1% @ ZI = 600Ω

220pF 10% 10VL @ Rp = 50Ω

220pF 10% 10V

7.5kΩ @Zlttx = 200Ω real

100nF 10% 10V (2)

@ Zlttx = 200Ω real

16.2kΩ @ VLOTTX = 340mVrms

100nF 10% 10V

@ τ = 3.2ms, RLV = 16.2kΩ

1.5nF 10% 10V

@fttx = 12kHz RLV = 16.2kΩ

(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.

(2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).

(3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula:

ZTTX=50*(Zlttx+2Rp).

(4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple.

(5) For low ripple application use 2x47µ F in parallel.

(6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).

(7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:

VBAT(ACTIVE)

VBATR(RING)

267kΩ

-46V

-62V

280kΩ

-48V

-65V

294kΩ

-49V

-68V

300kΩ

-50V

-70V

VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.).

The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the

current requested by the particular ringer load configuration.

(8) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3Ω

13/26

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