STM802TDS6E(2004) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM802TDS6E Datasheet PDF : 31 Pages
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STM690/704/795/802/804/805/806
Sym
Alter-
native
Description
Test Condition(1)
Min
Typ
Max Unit
Reset Thresholds
STM690T/ VCC Falling
3.00
3.075
3.15
V
704T/795T/
805T
VCC Rising
3.00
3.085
3.17
V
STM802T/ VCC Falling
3.00
3.075
3.12
V
804T/806T VCC Rising
3.00
3.085
3.14
V
VRST(10)
Reset Threshold
STM690S/ VCC Falling
2.85
2.925
3.00
V
704S/795S/
805S
VCC Rising
2.85
2.935
3.02
V
STM802S/ VCC Falling
2.88
2.925
3.00
V
804S/806S VCC Rising
2.88
2.935
3.02
V
STM690R/ VCC Falling
2.55
2.625
2.70
V
704R/795R/
805R
VCC Rising
2.55
2.635
2.72
V
STM802R/ VCC Falling
2.59
2.625
2.70
V
804R/806R VCC Rising
2.59
2.635
2.72
V
trec
RST Pulse Width
VCC < 3.6V
140
200
280 ms
Push-button Reset Input (STM704/806)
tMLMH
tMR
MR Pulse Width
100
20
ns
tMLRL tMRD
MR to RST Output Delay
60
500 ns
Watchdog Timer (NOT available on STM704/795/806)
tWD
Watchdog Timeout Period
VRST (max) < VCC < 3.6V
1.12
1.60
2.24
s
WDI Pulse Width
VRST (max) < VCC < 3.6V
100
20
ns
Chip-Enable Gating (STM795 only)
E-to-ECON Resistance
VCC = VRST (max)
46
Ω
E-to-ECON Propagation Delay
VCC = VRST (max)
2
7
ns
Reset-to-ECON High Delay
10
µs
ISC
ECON Short Circuit Current
VCC = 3.6V, Disable Mode,
ECON = 0V
0.1
0.75
2.0 mA
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = VRST (max) to 5.5V; and VBAT = 2.8V (except where noted).
2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT
can go to 0V if the other is greater than 2.0V.
3. VCC (min) = 1.0V for TA = 0°C to +85°C.
4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V.
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted
(output high impedance).
7. Not valid for STM795/804/805 (open drain).
8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.
9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75mV.
10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10mV (typ) hysteresis, which prevents internal
oscillation.
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