CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000
VV5410 & VV6410
Bit
5
6
7
Function
Default
Comment
FST/LST Enable/Tri-state
QCK Enable/Tri-state
Pre clock generator divide
On/Off
0
The FST/LST digital outputs can be tri-stated but are
enabled as outputs by default. The enabling/disabling
of FST/LST can be retimed to a field boundary. The
state of this control bit is always available via a serial
interface read, i.e. it does not have to wait to change
state at a field boundary
0
The QCK output can be tri-stated independently. The
enabling/disabling of QCK can be retimed to a field
boundary. The state of this control bit is always availa-
ble via a serial interface read, i.e. it does not have to
wait to change state at a field boundary.
0
The CIF and QCIF video modes expect a recom-
mended set of input clock frequencies, however the
acceptable range of clock frequencies can be extended
if this bit is set. If this bit is set then the primary input
clock will be divided down by 1.5 prior to the clock gen-
erator, thus if the expected clock input is 16 MHz, we
can set this bit and accept 24 MHz and achieve the
same final frame rate.
Table 40 : [22],[16] - data_format
OEB pin
0
0
1
1
data_format[5] oeb_composite
Comments
0
0
FST/LST outputs enabled.
1
1
FST/LST outputs are tri-stated by
data_format[5]
0
1
FST/LST outputs are tri-stated by OEB pin.
1
1
FST/LST outputs are tri-stated.
Table 41 : FST/LST output control
OEB pin
0
0
1
1
data_format[6] oeb_composite
Comments
0
0
QCK output enabled.
1
1
QCK output is tri-stated by op_format[6]
0
1
QCK output is tri-stated by OEB pin.
1
1
QCK output is tri-stated.
Table 42 : QCK output control
cd5410-6410f-3-0.fm
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