I²C Bus Selection
Reg.
Add.
Description
Slow Blanking TV SCART
Slow Blanking VCR SCART
Interrupt Flag
STV6413
Table 10: Output Signals (Read Mode)
Data
Bits
d7 d6 d5 d4 d3 d2 d1 d0
Comments
X X X X X X 0 1 Input < 2 V
2
X X X X X X 1 0 Input 16/9 format
X X X X X X 1 1 Input 4/3 format
X X X X 0 1 X X Input < 2 V
2
X X X X 1 0 X X Input 16/9 format
X X X X 1 1 X X Input 4/3 format
X X X 0 X X X X No change since read
1
X X X 1 X X X X One change has been
detected (refer to Note 1)
Note: 1 The Interrupt Flag will be cleared when this register is read. To prepare for a new interrupt, a “1”
must be re-written in the IT Enable bit (Reg. 04, d7).
3.2 Power-on Reset — Bus Register Initial Conditions
Power-on Reset is active when the supply VDD is less than 3.5 volts.
Non-significant bits (X) are pre-set to “0”.
Reg.
Data
Add. d7 d6 d5 d4 d3 d2 d1 d0
Comments
00h
0
0
0
0
0
0
0
0
Audio TV and Cinch outputs are in Stereo Mode, 0 dB Gain
Adjustment.
01h
0
0
0
0
0
0
0
0
TV, Cinch and VCR audio outputs are muted. VCR output is in Stereo
Mode.
02h 0 0 0 0 0 0 0 0 VCR, TV video outputs are muted.
03h
0
0
0
0
0
0
0
0
Fast Blanking is forced to ‘0’. RGB outputs are muted and in high
impedance.
04h 0 0 0 0 0 0 0 0 C_GATE is high. C_VCR is high impedance.
05h
0
0
0
0
0
0
0
0
Encoder and VCR R/Csub Bottom Level Clamp, RGB outputs 6 dB
Gain, and Slow Blanking parts are in read mode.
06h 0 0 0 0 0 0 0 0 All internal blocks are ON.
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