Bit
Bit
Number Mnemonic Description
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
2
T1X2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
1
T0X2 Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the
0
X2 peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Reset Value = X000 0000b
Not bit addressable
12 T89C51RD2
4243G–8051–05/03