External Data Memory Read
Cycle
ALE
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
TLLDV
TWHLH
TLLWL
TRLRH
TLLAX
A0-A7
TAVWL
TAVDV
TRLAZ
TRHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
TRHDZ
Serial Port Timing - Shift
Register Mode
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Symbol
Table 51. AC Parameters for a Fix Clock
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
-M
Min
Max
300
200
30
0
117
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
-L
Min
Max
300
200
30
0
117
Units
ns
ns
ns
ns
ns
90 T89C51RD2
4243G–8051–05/03