TDA7333 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TDA7333

RDS/RBDS processor

STMicroelectronics 

TDA7333N

Functional description

3.8.9

pllreg4 register

pllreg4

reset value

bit name

access

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0

0

0

0

1

1

0

0

LOCK LLOCK PLLEN PWDN DITEN FRAEN TEST1 TEST0

r

r r/w r/w r/w r/w r/w r/w

This bit is for internal test only.

This bit is for internal test only.

PLL factional mode enable (10).

1: Fractional mode enabled.

0: Fractional mode disabled.

PLL fractional dither enable (10).

1: Fractional dither enabled.

0: Fractional dither disabled.

Power down mode.

0: Normal mode

1: Power down mode. All clocks are stopped. This mode can only

be exit by hardware reset.

PLL enable. If this bit is set the PLL will be initialized with the values

of the pllreg4-0 registers. After PLL locking, the system clock (fsys)

is switched to the PLL output clock which must be 8.55 or 8.664

MHz. Clearing this bit will switch fsys back to the XTI clock.

PLL lost lock.

This bit is set if the PLL is used and loses lock. It will be cleared if

the PLL is disabled and enabled again.

PLL lock.

1: PLL is currently locked.

0: PLL is currently out of lock.

3.8.10

pllreg3 register

pllreg3

reset value

bit name

access

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0

0

0

0

0

1

1

0

- IDF4 IDF3 IDF2 IDF1 IDF0 ODF4 ODF3

r

r/w r/w r/w r/w r/w r/w r/w

bit 3 of PLL output divide factor (9) (10) (12).

bit 4 of PLL output divide factor (9) (10) (12).

bit 0 of PLL input divide factor (10) (12).

bit 1 of PLL input divide factor (10) (12).

bit 2 of PLL input divide factor (10) (12).

bit 3 of PLL input divide factor (10) (12).

bit 4 of PLL input divide factor (10) (12).

Not used.

3.8.11

pllreg2 Register

pllreg2

reset value

bit name

access

bit 7 bit 6 bit 5

1

1

1

ODF3 ODF1 ODF0

r/w

r/w

r/w

bit 4

0

MF6

r/w

bit 3

1

MF5

r/w

bit 2

0

MF4

r/w

bit 1

0

MF3

r/w

bit 0

1

MF2

r/w

(9) ODF value equal to zero is ignored, one is then used.

bit 2 of PLL multiplication factor (10) (11) (12).

bit 3 of PLL multiplication factor (10) (11) (12).

bit 4 of PLL multiplication factor (10) (11) (12).

bit 5 of PLL multiplication factor (10) (11) (12).

bit 6 of PLL multiplication factor (10) (11) (12).

bit 0 of PLL output divide factor (9) (10) (12).

bit 1 of PLL output divide factor (9) (10) (12).

bit 2 of PLL output divide factor (9) (10) (12).

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