TDA7563A
I2C bus
7.6
Acknowledge
The transmitter(*) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 31). The receiver(**) has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
(*) Transmitter
– master (µP) when it writes an address to the TDA7563A
– slave (TDA7563A) when the µP reads a data byte from TDA7563A
(**) Receiver
– slave (TDA7563A) when the µP writes an address to the TDA7563A
– master (µP) when it reads a data byte from TDA7563A
Figure 29. Data validity on the I2C bus
3$!
3#,
$!4! ,).%
34!",% $!4!
6!,)$
#(!.'%
$!4!
!,,/7%$
Figure 30. Timing diagram on the I2C bus
'!0'03
3#,
3$!
)#"53
34!24
34/0
Figure 31. Timing acknowledge clock pulse
'!0'03
3#,
3$!
34!24
-3"
!#+./7,%$'-%.4
&2/- 2%#%)6%2
'!0'03
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