I2C bus
TDA7563B
7.2.4
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 31). The receiver**, in order to acknowledge, has to pull-down (LOW) the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this
clock pulse.
* Transmitter
– master (P) when it writes an address to the TDA7563B
– slave (TDA7563B) when the P reads a data byte from TDA7563B
** Receiver
– slave (TDA7563B) when the P writes an address to the TDA7563B
– master (µP) when it reads a data byte from TDA7563B
Figure 29. Data validity on the I2C bus
3$!
3#,
$!4! ,).%
34!",% $!4!
6!,)$
#(!.'%
$!4!
!,,/7%$
Figure 30. Timing diagram on the I2C bus
'!0'03
3#,
3$!
)#"53
34!24
34/0
'!0'03
Figure 31. Timing acknowledge clock pulse
3#,
3$!
34!24
-3"
!#+./7,%$'-%.4
&2/- 2%#%)6%2
'!0'03
22/33
Doc ID 12733 Rev 6