M48Z09PC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48Z09PC

CMOS 8K x 8 ZEROPOWER SRAM

STMicroelectronics 

Figure 3. Block Diagram

M48Z09, M48Z19

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

POWER

VPFD

8K x 8

SRAM ARRAY

VCC

INT

VSS

A0-A12

DQ0-DQ7

E1

E2

W

G

AI01397

READ MODE

The M48Z09,19 is in the Read Mode whenever W

(Write Enable) is high, E1 (Chip Enable 1) is low,

and E2 (Chip Enable 2) is high. The device archi-

tecture allows ripple- through access of data from

eight of 65,536 locations in the static storage array.

Thus, the unique address specified by the 13 Ad-

dress Inputs defines which one of the 8,192 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within tAVQV (Address

Access Time) after the last address input signal is

stable, providing that the E1, E2, and G access

times are also satisfied. If the E1, E2 and G access

times are not met, valid data will be available after

the latter of the Chip Enable Access Times (tE1LQV

or tE2HQV) or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E1, E2 and G. If the outputs are

activated before tAVQV, the data lines will be driven

to an indeterminate state until tAVQV. If the Address

Inputs are changed while E1, E2 and G remain

active, output data will remain valid for tAXQX (Out-

put Data Hold Time) but will go indeterminate until

the next Address Access.

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

≤ 5ns

0 to 3V

1.5V

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 4. AC Testing Load Circuit

5V

DEVICE

UNDER

TEST

1kΩ

1.8kΩ

OUT

CL = 100pF or 30pF

CL includes JIG capacitance

AI01398

3/13

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