Z86E61(2008) View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z86E61 Datasheet PDF : 69 Pages
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Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
27
User Modes 4 and 5: EPROM and RAM Protect
To extend program security, EPROM and RAM protect cycles are provided for the
Z86E61/E63. Execution of the EPROM protect cycle prohibits proper execution of
the EPROM Read, EPROM Verify, and EPROM programming cycles. Execution
of the RAM protect cycle disables accesses to the upper 128 bytes of register
memory (excluding mode and configuration registers), but first the user’s program
must set bit 6 of the IMR (R251). Timing is shown in Figure 20 and Figure 21.
User Modes. Table 6 shows the programming voltage of each mode of the
Z86E61/E63.
Table 22. OTP Programminga
User/Test Mode
Device Pin No.
User Modes
EPROM Read
Program
Program Verify
EPROM Protect
RAM Protect
P33
VPP
VIH
VPPb
VPPb
VPPb
VPP
Device Pins
P32 P30 P31
EPM
VHc
X
X
VH
X
CE
VILd
VIL
VIL
VH
VH
OE
VIL
VIHe
VIL
VIH
VIH
P20
PGM
VIH
VIL
VIH
VIL
VIL
ADDR VCC
Addr 5.0V
Addr 6.0V
Addr
XXf
XXf
6.0V
6.0V
6.0V
Port 1
CNFG
Data
Out
In
Out
XX
XX
a. IPP during programming = 40 mA maximum.
ICC during programming, verify, or read = 40 mA maximum.
b. VPP = 12.0 ± 0.5 V.
c. VH = 12.0 ± 0.5 V
d. VIL = 0 V
e. VIH = 5 V.
f. XX = Irrelevant.
Z86E63 Signal Description for EPROM Program/Read
The following signals are required to correctly program or read the Z86E63
device.
ADDR
The address must remain stable throughout the program read cycle.
DATA
The I/O data bus must be stable during programming (OE High, PGM Low, VPP
High). During read the data bus outputs data.
PS014401-1001
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