QL6500-4PS672M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6500-4PS672M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Figure 26: Eclipse Input Register Cell

tIN, tINI

tICLK

tISU

+

-

tSID

QE

D

R

PAD

Symbol

tISU

tIHL

tICO

tIRST

tIESU

tIEH

Table 17: Input Register Cell

Parameter

Input register setup time: time the synchronous input of the pin must be stable

before the active clock edge

Input register hold time: time the synchronous input of the flip-flop must be

stable after the active clock edge

Input register clock to out: time taken by the flip-flop to output after the active

clock edge

Input register reset delay: time between when the flip-flop is “reset” (low) and

when the output is consequently “reset” (low)

Input register clock enable setup time: time “enable” must be stable before the

active clock edge

Input register clock enable hold time: time “enable” must be stable after the

active clock edge

Value

Min.

Max.

3.308 ns 3.526 ns

0 ns

-

-

0.494 ns

-

0.464 ns

0.830 ns 0.987 ns

0 ns

-

© 2007 QuickLogic Corporation

www.quicklogic.com

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