QL6500-7PB516I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL6500-7PB516I

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

Figure 35: I/O Banks with Relevant Pins

VCCIO (H)

INREF(H)

IOCTRL(H)

IO(H)

VCCIO (G)

INREF(G)

IOCTRL(G)

IO(G)

IO BANK A

IO BANK B

IO BANK F

IO BANK E

VCCIO (C)

INREF(C)

IOCTRL(C)

IO(C)

VCCIO (D)

INREF(D)

IOCTRL(D)

IO(D)

Recommended Unused Pin Terminations for the Eclipse Devices

All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the

Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the

Placement Editor, choose ConstraintÆFix Placement in the Option pull-down menu of SpDE.

The rest of the pins should be terminated at the board level in the manner presented in Table 24.

Signal Name

PLLOUT<x>

IOCTRL<y>

CLK/PLLIN<x>

PLLRST<x>

INREF<y>

Table 24: Recommended Unused Pin Terminations

Recommended Termination

For low power unused PLL output pins can be connected to VCC or GND so that their associated

input buffer never floats, otherwise PLL output pins can be left unconnected. Utilized PLL output

pins that route the PLL clock outside of the chip should not be tied to either VCC or GND.

Any unused pins of this type must be connected to either VCC or GND.

Any unused clock pins should be connected to VCC or GND.

If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC; under

normal operation, use it as needed. If PLLs are not used, the associated PLLRST pin must be

connected to the same voltage as VCCPLL (2.5 V or GND).

If an I/O bank does not require the use of INREF signal the pin should be connected to GND.

NOTE: x -> number, y -> alphabetical character.

© 2007 QuickLogic Corporation

www.quicklogic.com

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