TS4657 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TS4657
STMicroelectronics
TS4657 Datasheet PDF : 26 Pages
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TS4657
4
Application information
Application information
4.1
Serial audio interface
4.1.1
Master clock and data clocks
Three external clock signals are applied to the TS4657. The MCLK is the external master
clock applied by the audio data processor. The LRCLK is the channel frequency, also called
LEFT/RIGHT clock, at which the digital words for each channel are input to the device. The
LRCLK clock is the sample rate of the audio data. The ratio MCLK/LRCLK must be an
integer as shown in Table 9.
The BCLK is the bit clock and represents the clock at which the audio data is serially shifted
into the audio port. BCLK is linked to LRCLK. The minimum required BCLK frequency is
twice the audio sample rate times the number of bits in each audio word. Refer to Table 10
for the BCLK/LRCLK ratio.
MCLK, LRCLK and BCLK must be synchronous clock signals.
Table 9. Audio data sampling rates
LRCLK (kHz)
32
44.1
48
MCLK (MHz)
256x
8.192
11.2896
12.288
4.1.2
Digital audio input format
The TS4657 receives serial digital audio data through a 3-wire interface. SDAT is the serial
audio data input. The data is entered MSB first and is a two’s complement. The data can be
I2S, right or left justified. The data format is chosen with the control pins FORMAT1 and
FORMAT2 as detailed in Table 10.
Figure 50 on page 20 summarizes the implementation of the audio data format.
Table 10. Digital audio data formats supported by the TS4657
FORMAT2 FORMAT1
Data Format
BCLK/LRCLK ratio
Min
Max
0
0
Right-justified, 16-bit data
Data valid on rising edge of BCLK
32
256
0
1
Right-justified, 24-bit data
Data valid on rising edge of BCLK
48
256
1
0
Left-Justified, 16-bit up to 24-bit data
Data valid on rising edge of BCLK
2 x number of bits of data
256
I²S, 16-bit up to 24-bit data
1
1
2 x number of bits of data
256
Data valid on rising edge of BCLK
19/26
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