TS80C31X2
VCC
ICC
VCC
VCC
Reset = Vss after a high pulse
P0
during at least 24 clock cycles
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 10. Operating ICC Test Condition
VCC
ICC
VCC
VCC
Reset = Vss after a high pulse
P0
during at least 24 clock cycles
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 11. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST EA
(NC)
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 12. ICC Test Condition, Power-Down Mode
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL
TCLCH
TCLCH = TCHCL = 5ns.
Figure 13. Clock Signal Waveform for ICC Tests in Active and Idle Modes
30
Rev. C - 15 January, 2001