TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
VCC
ICC
VCC
VCC
Reset = Vss after a high pulse
P0
during at least 24 clock cycles
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 21. Operating ICC Test Condition
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
VCC
ICC
VCC
VCC
P0
EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 22. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST EA
(NC)
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 23. ICC Test Condition, Power-Down Mode
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL
TCLCH
TCLCH = TCHCL = 5ns.
Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes
Rev. C - 06 March, 2001
61