VG36128801BTL-8H View Datasheet(PDF) - Vanguard International Semiconductor

Part Name

Description

Manufacturer

VG36128801BTL-8H

CMOS Synchronous Dynamic RAM

Vanguard International Semiconductor 

VIS

VG36128401BT / VG36128801BT / VG36128161BT

CMOS Synchronous Dynamic RAM

10.2 PRECHARGE TERMINATION

10.2.1 PRECHARGE TERMINATION in READ Cycle

During READ cycle, the burst read operation is terminated by a precharge command.

When the precharge command is issued, the burst read operation is terminated and precharge starts.

The same bank can be activated again after tRP from the precharge command.

When CAS latency is 2, the read data will remain valid until one clock after the precharge command.

When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.

Precharge Termination in READ Cycle

T0

T1

CLK

Command

Read

CAS latency=2

DQ

Burst lengh= X

T2

T3

T4

T5

T6

T7

T8

PRE

tRP

ACT

Q0

Q1

Q2

Q3

Hi-Z

command

CAS latency=3

DQ

Read

PRE

Q0

Q1

tRP

Q2

Q3

ACT

Hi-Z

Document :1G5-0183

Rev.1

Page 25

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