CS8401A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS8401A Datasheet PDF : 34 Pages
| |||
CS8402A
When FSYNC is a word clock (Format 2), CBL
is sampled when left C,U,V are sampled. When
FSYNC is Left/Right, CBL is sampled when left
C,U,V are sampled. The channel status block
boundary is reset when CBL transitions from
low to high (based on two successive samples of
CBL). MCK for the CS8402A is normally ex-
pected to be 128 times the sample frequency, in
the transparent mode MCK must be 256 Fs.
Professional Mode
Setting PRO low places the CS8402A in profes-
sional mode as shown in Figure 19. In
professional mode, channel status bit 0 is trans-
mitted as a one and bits 1, 2, 3, 4, 6, 7, and 9
can be controlled via dedicated pins. The pins
are actually the inverse of the identified bit. For
example, tying the C1 pin low places a one in
channel status bit 1. As shown in the Application
Note, Overview of AES/EBU Digital Audio In-
terface Data Structures, C1 indicates
audio/non-audio; C6 and C7 determine the sam-
ple frequency; and C9 allows the encoded
channel mode to be stereophonic. EM1 and EM0
determine emphasis and encode C2, C3, C4 as
SDATA 8
SCK 6
FSYNC 7
M2 M1 M0
23 22 21
Serial
Port
Logic
C 10
U 11
9
V
Registers
TRNPT
24
2 14 13 3 4 1 12
PRO EM0 EM1 C1 C6 C7 C9
shown in Table 4. The dedicated channel status
pins are read at the appropriate time and are
logically OR’ed with data input on the channel
status port, C. In Transparent Mode, these dedi-
cated channel status pins are ignored; and
channel status bits are input at the C pin.
The channel status data cyclic redundancy check
character (C.S. byte 23) is always generated in-
dependently for channels A and B and is
transmitted at the end of the channel status
block.
Data should not be input through the channel status
port, C, during the CRCC byte time frame, since in-
puts on C are logically OR’ed with internally
generated data.
Consumer Mode
Setting PRO high places the CS8402A in consumer
mode which redefines the pins as shown in Fig-
ure 20. In consumer mode, channel status bit 0 is
transmitted as a zero and channel status bits 2, 3, 8,
9, 15, 24, and 25 are controlled via dedicated pins.
The pins are actually the inverse of the bit so if pin
Audio
Aux
C Bits
CRC
U Bits
Validity
Preamble
Parity
Biphase
Mux
Mark
Encoder
20
Line
Driver
17
TXP
TXN
Timing
16
RST
15 5
CBL MCK
Figure 19. CS8402A Block Diagram - Professional Mode
22
DS60F1
Share Link: 