XE8802MI000 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

XE8802MI000

Sensing Machine Data Acquisition SoC with 16+10 bit ZoomingADC™ Embedded RISC controller and LCD driver

Semtech Corporation 

XE8802 Sensing Machine Data Acquisition MCU

with ZoomingADC™ and LCD driver

The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in

the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values.

In order to have glitch free outputs, the PWM outputs on PB(0) and PB(1) are sampled versions of these internal

PWM signals, therefore delayed by one counter clock cycle.

The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.

PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the

counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in

cascaded mode are shown in Table 20-14. Choosing a 16 bit PWM code which is higher than the maximum value

that can be represented by the number of bits chosen for the resolution results in a PWM output which is always

tied to 1.

PwmXsize(1:0)

11

10

01

00

Resolution

16 bits

14 bits

12 bits

10 bits

Table 20-14: Resolution selection in cascaded PWM mode

Small PWM code

Large PWM code

Tls m all

Ths m all

Tllarge

Thlarge

Tper

Figure 20-3: PWM modulation examples

The period of the PWM signal is given by the formula:

Tper = 2resolution

f ckcnt

The duty cycle ratio DCR of the PWM signal is defined as:

DCR = Th

Tper

100

DCR can be selected between

% and 100 %.

2 resolution

DCR in % in function of the RegCntX content(s) is given by the relation:

DCR

=

MIN

⎜⎛

⎝

100(1 + RegCntX

2 resolution

)

,100

⎟⎞

⎠

© Semtech 2006

20-9

www.semtech.com

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