XE8802MI000 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

Manufacturer

XE8802MI000

Sensing Machine Data Acquisition SoC with 16+10 bit ZoomingADC™ Embedded RISC controller and LCD driver

Semtech Corporation 

XE8802 Sensing Machine Data Acquisition MCU

with ZoomingADC™ and LCD driver

4.3.9

Interrupt handler (h0040-h0047)

Name

Address

7

RegIrqHig IrqAC

h0040

rc1,0,glob

RegIrqMid UsrtCond2

h0041

rc1,0,glob

RegIrqLow PAIrq[7]

h0042

rc1,0,glob

RegIrqEnHig

h0043

RegIrqEnMid

h0044

RegIrqEnLow

h0045

RegIrqPriority

h0046

RegIrqIrq

h0047

r0

6

128Hz

rc1,0,glob

UrstCond1

rc1,0,glob

PAIrq[6]

rc1,0,glob

r0

5

IrqSPI

rc1,0,glob

PAIrq[5]

rc1,0,glob

CntIrqB

rc1,0,glob

r0

Table 4-4-11. Interrupt handler registers

4

3

CntIrqA CntIrqC

rc1,0,glob rc1,0,glob

PAIrq[4]

1Hz

rc1,0,glob rc1,0,glob

CntIrqD PAIrq[3]

rc1,0,glob rc1,0,glob

IrqEnHig[7:0]

rw,0000000,glob

IrqEnMid[7:0]

rw,0000000,glob

IrqEnLow[7:0]

rw,0000000,glob

IrqPriority[7:0]

r,11111111,glob

r0

r0

2

CmpdIrq

rc1,0,glob

VldIrq

rc1,0,glob

PAIrq[2]

rc1,0,glob

IrqHig

r,0,glob

1

UartIrqTx

rc1,0,glob

PAIrq[1]

rc1,0,glob

r0

IrqMid

r,0,glob

0

UartIrqRx

rc1,0,glob

PAIrq[0]

rc1,0,glob

r0

IrqLow

r,0,glob

The origin of the different interrupts is summarised in the table below.

Event

CmpdIrq

CntIrqA

CntIrqB

CntIrqC

CntIrqD

128Hz

1Hz

PAIrq[7:0]

UartIrqRx

UartIrqTx

UrstCond1

UsrtCond2

VldIrq

IrqAC

IrqSPI

Event source

Low power comparators

Counter/Timer A (counter block)

Counter/Timer B (counter block)

Counter/Timer C (counter block)

Counter/Timer D (counter block)

Low prescaler (clock block)

Low prescaler (clock block)

Port A

UART reception

UART transmission

USRT condition 1

USRT condition 2

Voltage level detector

Acquisition chain end of conversion interrupt

SPI end of reception/transmission interrupt

Table 4-4-12. Interrupt source description

4.3.10 USRT (h0048-h004F)

Name

Address

7

6

5

RegUsrtS1

h0048

r0

r0

r0

RegUsrtS0

h0049

r0

r0

r0

RegUsrtCond1

h004A

r0

r0

r0

RegUsrtCond2

h004B

r0

r0

r0

RegUsrtCtrl

h004C

r0

r0

r0

RegUsrtBufferS1

h004D

r0

r0

r0

RegUsrtEdgeS0

h004E

r0

r0

r0

Table 4-4-13. USRT register description

4

3

2

1

0

UsrtS1

r0

r0

r0

r0

s,1,glob

UsrtS0

r0

r0

r0

r0

s,1,glob

UsrtCond1

r0

r0

r0

r0

rc,0,glob

UsrtCond2

r0

r0

r0

r0

rc,0,glob

UsrtWaitS0 UsrtEnWaitCond1 UsrtEnWaitS0 UsrtEnable

r0

r,0,glob rw,0,glob rw,0,glob rw,0,glob

UsrtBufferS1

r0

r0

r0

r0

r,0,glob

UsrtEdgeS0

r0

r0

r0

r0

r,0,glob

© Semtech 2006

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4-7

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