XE8805AMI000 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
XE8805AMI000 Datasheet PDF : 156 Pages
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XE8805/05A
Register name
r0
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
Register function
general purpose
general purpose
general purpose
data memory offset
MSB of the data memory index i0
LBS of the data memory index i0
MSB of the data memory index i1
LBS of the data memory index i1
MSB of the data memory index i2
LBS of the data memory index i2
MSB of the data memory index i3
LBS of the data memory index i3
MSB of the program memory index ip
LBS of the program memory index ip
status register
accumulator
Table 3-1. CPU internal register definition
bit name function
7 IE2 enables (when 1) the interrupt request of level 2
6 IE1 enables (when 1) the interrupt request of level 1
5 GIE enables (when 1) all interrupt request levels
4 IN2 interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
3 IN1 interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
2 IN0 interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
1 EV1 event request of level 1. The events labelled “low” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
0 EV0 event request of level 1. The events labelled “hig” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
Table 3-2. Status register description
The CPU also has a number of flags that can be used for conditional jumps. These flags are defined in Table 3-3.
symbol
Z
C
V
name
zero
carry
overflow
function
Z=1 when the accumulator a content is zero
This flag is used in shift or arithmetic operations.
For a shift operation, it has the value of the bit that was shifted out (LSB for shift
right, MSB for shift left).
For an arithmetic operation with unsigned numbers:
it is 1 at occurrence of an overflow during an addition (or equivalent).
it is 0 at occurrence of an underflow during a subtraction (or equivalent).
This flag is used in shift or arithmetic operations.
For arithmetic or shift operations with signed numbers, it is 1 if an overflow or
underflow occurs.
Table 3-3. Flag description
© Semtech 2006
www.semtech.com
3-3
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