XRT83SL30IV(2003) View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
XRT83SL30IV
(Rev.:2003)
(Rev.:2003)
Exar Corporation
XRT83SL30IV Datasheet PDF : 76 Pages
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XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.4
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION
D3
JASEL1 Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are R/W
0
used to disable or place the jitter attenuator in the transmit or
receive path.
JASEL1
bit D3
0
0
1
1
JASEL0
bit D2
JA Path
0
JA Disabled
1
JA in Transmit Path
0
JA in Receive Path
1
JA in Receive Path
D2
JASEL0 Jitter Attenuator select bit 0: See description of bit D3 for the R/W
0
function of this bit.
D1
JABW Jitter Attenuator Bandwidth Select:
R/W
0
In E1 mode, set this bit to "1" to select a 1.5Hz Bandwidth for the
Jitter Attenuator In E1 mode. The FIFO length will be automati-
cally set to 64 bits.
Set this bit to "0" to select 10Hz Bandwidth for the Jitter Attenua-
tor in E1 mode.
In T1 mode the Jitter Attenuator Bandwidth is permanently set to
3Hz, and the state of this bit has no effect on the Bandwidth.
Mode
T1
T1
T1
T1
E1
E1
E1
E1
JABW
bit D1
0
0
1
1
0
0
1
1
FIFOS_n
bit D0
0
1
0
1
0
1
0
1
JA B-W
Hz
3
3
3
3
10
10
1.5
1.5
FIFO
Size
32
64
32
64
32
64
64
64
D0
FIFOS FIFO Size Select: See table of bit D1 above for the function of
R/W
0
this bit.
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