Z380 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z380

MICROPROCESSOR

Zilog 

ZILOG

EXTERNAL INTERFACE (Continued)

Miscellaneous Timing

There are two cases where a specific transaction is not

taking place on the bus which are illustrated in this section:

the bus idle cycle and the I/O heartbeat cycle.

MICROPROCESSOR

Idle Cycles

When no transactions are being performed on the bus, an

idle cycle occurs (Figure 16). All control signals, for both

memory and I/O, are inactive during the Idle cycle.

TiH

TiL

BUSCLK

ADDRESS

DATA

STATUS

/WAIT

/MSIZE

/TREFR

/TREFA

/TREFC

/MRD

/MWR

Figure 16. Idle Cycle

PS010001-0301

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