Z8018010FSG View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z8018010FSG Datasheet PDF : 85 Pages
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Z80180
Microprocessor Unit
71
4. The refresh address is incremented by one for each successful refresh cycle, not for each
refresh. Independent of the number of missed refresh requests, each refresh bus cycle
uses a refresh address incremented by one from that of the previous refresh bus cycles.
MMU Common Base Register
Mnemonic CBR
Address 38
MMU Common Base Register (CBR)—CBR specifies the base address (on 4-KB
boundaries) used to generate a 20-bit physical address for Common Area 1 accesses. All bits
of CBR are reset to 0 during RESET.
MMU Bank Base Register (BBR: I/O Address = 39h)
7
6
5
4
3
2
1
0
Bit
CB7
CB6 CB5
CB4
CB3
CB2
CB1
CB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 73. MMU Bank Base Register (BBR: I/O Address = 39h)
MMU Bank Base Register (BBR)
Mnemonic BBR
Address 39
BBR specifies the base address (on 4-KB boundaries) used to generate a 19-bit physical
address for Bank Area accesses. All bits of BBR are reset to 0 during RESET.
MMU Bank Base Register (BBR: I/O Address = 39h)
7
6
5
4
3
2
1
0
Bit
BB7
BB6 BB5 BB4
BB3
BB2
BB1
BB0
R/W
R/W R/W
R/W
R/W
R/W
R/W
R/W
Figure 74. MMU Bank Base Register (BBR: I/O Address = 39h)
PS014004-1106
Architecture
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