Z86L997SZ008SC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z86L997SZ008SC

Low-Voltage Microcontrollers with ADC

Zilog 

Z86D990/Z86D991 OTP and Z86L99X ROM

Low-Voltage Microcontrollers with ADC

18

Figure 10. IRQ Logic

Internal interrupt requests are sampled during the most recent clock cycle before

an Op Code fetch (see Figure 11.) External interrupt requests are sampled two

internal clocks earlier than internal interrupt requests because of the synchroniz-

ing flip-flops shown in Figure 9.

Figure 11. Interrupt Request Timing

At sample time, the interrupt request is transferred to the second flip-flop shown in

Figure 10, which drives the interrupt mask and priority logic. When an interrupt

cycle occurs, this flip-flop is reset only for the highest priority level that is enabled.

The user has direct access to the second flip-flop by reading and writing to the

IRQ. The IRQ is read by specifying it as the source register of an instruction, and

the IRQ is written by specifying it as the destination register.

Interrupt Initialization

After RESET, all interrupts are disabled and must be re-initialized before vectored

or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt

Mask Register, and Interrupt Request Register must be initialized, in that order, to

PS003807-1002

PRELIMINARY

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