Z893232YFEC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z893232YFEC

16-BITDIGITAL SIGNALPROCESSORS

Zilog 

PRELIMINARY

RAM ADDRESSING

The address of the RAM is specified in one of three ways (Figure 22):

RAM Pointers

P0:0

P1:0

%37

P2:0

%FF

@P1:0

RAM0

256 x 16-Bit

%37

%0321

RAM1

%FF

256 x 16-Bit

%0321

%04

Z89323/373/393

16-BIT DIGITAL SIGNAL PROCESSORS

RAM Pointers

P0:1

P1:1

P2:1

S4 / S3 = 01

%00

%1FFF

Internal ROM

4K x 16-Bit

%00

D0:0

D1:0

D2:0

D3:0

Data Pointers

%0321

D0:1

D1:1

D2:1

D3:1

@@P1:0

%0321

%1234

%0000

@D0:1

Each of the following instructions

load %1234 into the Accumulator:

LD A,@@P1:0

LD A,@D0:1

Figure 31. RAM, ROM, and Pointer Architecture

Register Indirect

Pn:b n = 0-2, b = 0-1

The most commonly used method is a register indirect

addressing method, where the RAM address is specified

by one of the three RAM address pointers (n) for each bank

(b). Each source/destination field in Figures 6 and 9 may

be used by an indirect instruction to specify a register

pointer and its modification after execution of the instruction.

b

n1 n0

D8 D3 D2 D1 D0

RAM Pointer Register

Operation

RAM Bank

Figure 32. Indirect Register

DS95DSP0101 Q4/95

39

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