Z8018933ASC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018933ASC

GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog 

Zilog

PRELIMINARY

Z80189/Z8L189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

DOUBLE BUFFERING FOR THE TRANSMITTER IN 16450 MODE (Continued)

Host Write

Empty/Full

Host & MPU THRE = 1 0

16450

THR

Register

Empty/Full

(MPU TEMT) TSRE = 1 0

THR to TSR

delay

transfer

Byte Transfer if:

- THRE=0; and

- TSRE = 1; and

- Character delay timer is timed out.

TSR

Transmit

Shift Reg.

Emulation

Note: Timer reloads and counts down

whenever data is transferred from THR to TSR.

Added TSR Buffer for the

transmit data

Host TEMT = 1 if - THRE = 1 and

- TSRE = 1 and

- Emulation delay timer is timed out

Note: MPU sees TSR bit in the LSR Register as TEMT bit

Figure 79. TEMT Emulation Logic Implementation

Z80189 MIMIC DMA Consideration

Z80189 MIMIC Design Hint

Since the /HRXRDY and /HTXRDY is removed in the Z189,

the MIMIC DMA feature found on the Z182 is not available

on the Z189.

The MIMIC output drive capability has been increased to

16 mA on the Z189. This may eliminate the need for

buffering to the PC Bus.

70

DS971890301

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