DSM2190F4
Table 25. AC Symbols for PLD Timing
Signal Letters
A
Address Input
C CEout Output
D Input Data
E
E Input
N Reset Input or Output
P
Port Signal Output
Q Output Data
R RD Input (read)
S
Chip Select Input, BMS, DMS, IOMS, or FSx
W WR Input (write)
B
VSTBY Output
M Output Macrocell
Example: tAVWL – Time from Address Valid to
Write input Low.
Signal Behavior
t
Time
L
Logic Level Low
H
Logic Level High
V
Valid
X
No Longer a Valid Logic Level
Z
Float
PW Pulse Width
Figure 28. Switching Waveforms – Key
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
DON'T CARE
OUTPUTS ONLY
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
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