TSA1005-20IF View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TSA1005-20IF

DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER

STMicroelectronics 

TSA1005

Operating conditions of the evaluation board:

Find below the connections to the board for the

power supplies and other pins:

board

notation

connection

internal

voltage (V)

external

voltage (V)

AV

AVCC

2.5

AG

AGND

0

RPI

REFPI

0.88

0.94 to 1.4

RMI

REFMI

0 to 0.4

CMI

INCMI

0.46

0.2 to 1

RPQ

REFPQ

0.88

0.94 to 1.4

RMQ

REFMQ

0 to 0.4

CMQ

INCMQ

0.46

0.2 to 1

DV

DVCC

2.5

DG

DGND

0

GB1

GNDBI

0

VB1

VCCBI

2.5

GB2

GNDBE

0

VB2

VCCBE

2.5/3.3

GB3

GNDB3

0

VB3

VCCB3

2.5

Care should be taken for the evaluation board

considering the fact that the outputs of the con-

verter are 2.5V/3.3V (VB2) tolerant whereas the

74LCX573 external buffers are operating up to

2.5V.

The ADC outputs on the connector J6 are D11

(MSB) to D2 (LSB).

Single and Differential Inputs:

The ADC board components are mounted to test

the TSA1005 with single analog input; the

ADT1-1WT transformer enables the differential

drive into the converter; in this configuration, the

resistors RSI6, RSI7, RSI8 for I channel (respec-

tively RSQ6, RSQ7, RSQ8 for Q one) are con-

nected as short circuits whereas RSI5, RSI9 (re-

spectively RSQ5, RSQ9) are open circuits.

The other way is to test it via JI1 and JI1B differen-

tial inputs. So, the resistances RSI5, RSI9 for I

channel (respectively RSQ5, RSQ9 for Q one) are

connected as short circuits whereas RSI6, RSI7,

RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q

one) are open circuits.

Grounding consideration

So as to better reject noise on the board, connect

on the bottom overlay AG (AGND), DG(DGND),

GB1(GNDBI) together from one part, and

GB2(GNDBE) with GB3(GNDB3) from the other

part.

Mode select

So as to evaluate a single channel or the dual

ones, you have to connect on the board the

relevant position for the SELECT pin.

With the strap connected:

- to the upper connectors, the I channel at the out-

put is selected.

- horizontally, the Q channel at the output is se-

lected.

- to the lower connectors, both channels are se-

lected, relative to the clock edge.

Figure 9: mode select

SELECT

I channel

SELECT

Q channel

CLK DGND DVCC

I/Q channels

schematic

board

Consumption adjustment

Before any characterization, care should be taken

to adjust the Rpol (Raj1) and therefore Ipol value

in function of your sampling frequency.

18/22

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