AT91SAM9CN12B-CFUR View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9CN12B-CFUR

ARM-based Embedded MPU

Atmel Corporation 

 ‘I’/’O’

Indicates whether the signal is input or output state.

 “PU”/”PD”

Indicates whether Pull-up or Pull-down, or nothing is enabled.

 “ST”

Indicates if Schmitt Trigger is enabled.

Note:

Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as

an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with

Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down.

8.4.2

PIO Line Selection

Peripheral A, B or C is selected thanks to the PIO_ABCDSR1 and PIO_ABCDSR2 registers in the PIO Controller

Interface.

Table 8-2. PIO Line Selection

Px value in PIO_ABCDSR2

0

0

1

Px value in PIO_ABCDSR1

0

1

0

A, B or C

A

B

C

8.5 Fuse Box Features

SAM9CN12 embeds 320 One Time Programming (OTP) bits. When the OTP bit is set, it is seen as ‘1’. The user interface

allows the user to perform the following operations:

8.5.1

Read

 10 registers SR0-SR9 that reflect OTP bit state

 MSK field (write-once) allow user to mask registers SR1 to SR9

 All OTP bits are read as ‘1’ when VDDFUSE is floating, all security features are set.

8.5.2

Write

 Done in one 32-bit DATA register

 SEL field to select the 32-bit word 0 to 9

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 32

11063K–ATARM–05-Nov-13

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