AT91SAM9N12-CFU View Datasheet(PDF) - Atmel Corporation
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AT91SAM9N12-CFU Datasheet PDF : 1104 Pages
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Table 9-2. ARM Instruction Mnemonic List (Continued)
Mnemonic Operation
Mnemonic
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDRH
Load Half Word
STRH
LDRB
Load Byte
STRB
LDRBT
Load Register Byte with
Translation
STRBT
LDRT
Load Register with
Translation
STRT
LDM
Load Multiple
STM
SWP
Swap Word
SWPB
MCR
Move To Coprocessor
MRC
LDC
Load To Coprocessor
STC
CDP
Coprocessor Data
Processing
Operation
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with
Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
9.4.10 New ARM Instruction Set
.
Table 9-3. New ARM Instruction Mnemonic List
Mnemonic Operation
Mnemonic
BXJ
Branch and exchange to
Java
MRRC
BLX (1)
Branch, Link and exchange
MCR2
SMLAxy
SMLAL
SMLAWy
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
MCRR
CDP2
BKPT
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy Signed Multiply 32 * 16 bit
STRD
QADD
Saturated Add
STC2
QDADD
Saturated Add with Double
LDRD
QSUB
Saturated subtract
LDC2
QDSUB
Saturated Subtract with
double
CLZ
Operation
Move double from
coprocessor
Alternative move of ARM reg
to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory
prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Alternative Load to
Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 41
11063K–ATARM–05-Nov-13
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