AT91SAM9CN12B-CFUR View Datasheet(PDF) - Atmel Corporation
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AT91SAM9CN12B-CFUR Datasheet PDF : 1104 Pages
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9.5 CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:
ARM9EJ-S
Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
To control these features, CP15 provides 16 additional registers. See Table 9-5.
Table 9-5. CP15 Registers
Register
0
0
Name
ID Code(1)
Cache type(1)
Read/Write
Read/Unpredictable
Read/Unpredictable
0
TCM status(1)
Read/Unpredictable
1
Control
Read/write
2
Translation Table Base
Read/write
3
Domain Access Control
Read/write
4
Reserved
None
5
Data fault Status(1)
Read/write
5
Instruction fault status(1)
Read/write
6
Fault Address
Read/write
7
Cache Operations
Read/Write
8
TLB operations
Unpredictable/Write
9
cache lockdown(2)
Read/write
9
TCM region
Read/write
10
TLB lockdown
Read/write
11
Reserved
None
12
Reserved
None
13
FCSE PID(1)
Read/write
13
Context ID(1)
Read/Write
14
Reserved
None
15
Test configuration
Read/Write
Notes: 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed
depends on the value of the opcode_2 field.
2. Register location 9 provides access to more than one register. The register accessed depends on the value
of the CRm field.
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 43
11063K–ATARM–05-Nov-13
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