PIC16C554T-IPT View Datasheet(PDF) - Microchip Technology
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PIC16C554T-IPT Datasheet PDF : 108 Pages
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4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC<12:8>) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> PCH). The lower exam-
ple in Figure 4-6 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> PCH).
FIGURE 4-6:
LOADING OF PC IN
DIFFERENT SITUATIONS
12
PC
PCH
PCL
87
PCLATH<4:0>
5
0
8
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12 11 10
PC
87
2 PCLATH<4:3>
PCL
0
GOTO, CALL
11
Opcode <10:0>
PCLATH
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2 STACK
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
PIC16C55X
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
4.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
NEXT
movlw
movwf
clrf
incf
btfss
goto
CONTINUE:
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 21
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